Many analog-to-digital converters (ADC) are implemented in a pipeline architecture. Multi-stage or pipeline ADC's comprise a plurality of stages that quantize samples of an analog input signal at successively refined resolutions. Generally, the first stage receives an analog signal to be digitized and both outputs some number of the most significant bits (MSB) of the digitized output, and provides a residue signal to the next stage in the pipeline. The residue signal is related to the difference between the digital output bits generated by each stage and the analog signal provided to each respective stage.
The residue signal indicates the quantization error of a stage and is provided as the input analog signal to a subsequent stage. The subsequent stage converts the residue signal into a number of the next most significant bits of the digitized output and provides a residue signal to the subsequent stage in the pipeline. This process is repeated until the final stage of the pipeline, operating on the residue of the previous stage, outputs the least significant bits of the digitized output. Accordingly, the digitized output (i.e., the digital representation of a sample of the analog input signal) typically includes digital output bits from each of the stages in the pipeline.
Pipeline architectures typically have relatively inexpensive hardware costs compared to other ADC implementations (e.g., by reducing the number of comparators required in other parallel architectures) and exhibit generally satisfactory throughput. However, speed, accuracy and resolution of the ADC may be limited by the pipeline architecture. In particular, the accuracy and resolution of a pipeline ADC may be effected by offset errors, gain errors, integral non-linearity (INL) errors, differential non-linearity (DNL) errors, etc. Various calibration techniques have been employed to correct for these errors. However, calibrating one or more of these errors at a resolution higher than the resolution of the digital output signal provided by the ADC often is problematic. For example, the resolution of an ADC (which is related to the number of bits provided by the ADC) is often limited by the number of pipeline stages arranged as described above that can provide additional digitized outputs that are correlated enough to the stage's input analog to provide further information. Accordingly, the digital output bits are often truncated at the last meaningful stage of the pipeline. However, errors in the pipeline may exist at resolutions higher than the resolution of the ADC. That is, errors may exist at smaller increments than can be described by the least significant bit provided by the pipeline, making such errors difficult to account for and correct.